Chip Research: 2.5D Power, CFET Scaling, 3D IC Debug

• Washington State and Wisconsin researchers tackle voltage droop in 2.5D chiplet architectures
• Imec questions 2D CFET pitch scaling advantage at A2 node
• Google, Delft solve 3D IC debug with novel hardware approach
• NVIDIA, Duke deploy self-supervised AI to fix advanced-node layout violations

A batch of semiconductor research papers published this month reveals active work on problems that won’t hit production for years—but are already forcing hard design tradeoffs. Washington State University and the University of Wisconsin–Madison released a paper on controlling voltage droop in 2.5D processing-in-memory chiplet architectures, a challenge that becomes acute when sub-1V supply rails meet high-current AI workloads spread across multiple dies on an interposer.

Conventional planar power delivery on XPU cards suffers from high I²R loss in the “last-millimeter” power delivery when serving the extreme current demands of AI training. With 48V replacing 12V bus voltage, efficient high-density power conversion has become one of the main bottlenecks for system integration, a shift that puts pressure on both converter topologies and the vertical power delivery networks enabled by 2.5D and 3D packaging.

Contact pitch limits 2D CFET scaling at A2 node

Imec’s paper on gate-all-around 2D complementary FETs asks whether the architecture delivers on its promise at the A2 node and beyond. The answer is more nuanced than expected. Researchers developed an A2-oriented 2D CFET integration flow with a contacted poly pitch of 36 nm and gate length of 10 nm, but despite their atomically thin channels, 2D GAA CFETs do not provide a contacted poly pitch scaling advantage over silicon GAA CFETs at the A2 node because contact formation constraints impose a similar minimum CPP of 36 nm.

The finding matters because 2D materials have been positioned as the solution to channel thickness constraints below 10 nm gate length. The continuous reduction of gate and channel length requires ever thinner semiconductor channels to restrict current flow pathways and limit charge carrier leakage when the device is off; to move CFET transistors into the A2 node with channel lengths below 10 nm, silicon channel thickness should also shrink below 10 nm. But if contact pitch—not channel physics—becomes the binding constraint, the material advantage narrows considerably.

This points to a broader reality in angstrom-era scaling: parasitics and interconnect resistance often dictate performance more than intrinsic device speed. Imec foresees CFET introduction from the A7 node onwards, extending the technology roadmap to at least the A3 generation, but the contact co-optimization work suggests that process integration complexity, not just transistor physics, will determine when and whether 2D materials make economic sense in volume manufacturing.

Interposer enables system-level debug on stacked DRAM

Researchers from Google and Delft University of Technology published a paper presenting a novel failure analysis hardware and sample preparation solution that enables system-level FA on mobile SoC PoP devices, where DRAM is stacked atop the logic controller. The hardware solution overcomes the challenge of connecting DRAM atop the SoC silicon using the smallest possible interposer pin pitch of approximately 210 µm, with an advanced DRAM card design that enables data rates up to 6.3 Gbps using DDR training and runs standard Android stress applications.

The work addresses a known pain point in 3D IC development. 3D ICs offer improved performance, reduced power consumption, and increased functionality, but the increased complexity introduced by stacking multiple dies vertically presents significant challenges for verification, as traditional methodologies are inadequate due to intricate interactions between stacked dies, including thermal effects, through-silicon vias, and inter-die signaling. Providing direct line-of-sight access to the bottom die while preserving top-die functionality is the kind of mundane, non-glamorous problem that can derail an entire product if not solved early.

Self-supervised AI fixes design rule violations

NVIDIA and Duke University contributed a paper on self-supervised constraint-aware layout generation to fix design rule violations at advanced nodes. The work tackles the reality that as geometries shrink, DRV fixing becomes a bottleneck in place-and-route closure, especially for local optimization where manual intervention is impractical at scale.

Other papers in the roundup include National Taiwan University’s work on defect prediction frameworks spanning lithography, EUV, and nanoimprint; A*STAR’s joint optimization of chiplet placement and interposer footprint for 2.5D systems; and Texas A&M and Korea’s KIMM collaboration on self-focusing control for depth-precise wafer slicing of 4H-SiC using femtosecond laser processing. The latter addresses silicon carbide processing challenges that constrain power semiconductor manufacturing throughput.

Article Source: Chip Industry Technical Paper Roundup: Aug. 18