- Muse Semiconductor and True Circuits partner on university PLL IP access program
- TCI General Purpose PLLs offered in TSMC 180nm, 65nm, 28nm, 16nm
- Program mirrors commercial IP deployment with NDAs and foundry compliance
- Self-service portal includes AI-assisted knowledge base for PLL questions
Muse Semiconductor and True Circuits launched a university access program this week that bundles commercial phase-locked loop (PLL) IP with multi-project wafer (MPW) services at discounted rates. The program offers TCI PLL hard macros in select TSMC processes to students and researchers using Muse MPW services, with the goal of enabling students and faculty to conduct more impactful research by using silicon-proven commercial IP.
Bill Isaacson, General Manager of Muse Semiconductor, described the program as an opportunity for universities to access world-class PLL IP while enhancing the overall MPW tapeout service experience. Brian Gardner, V.P. of Business Development at True Circuits, noted the initiative supports the growing number of students taking undergraduate courses that build chips and aligns with the company’s open-sourcing of its AMS development software, JDE.
Program replicates commercial IP workflows with academic pricing
The University IP Access Program is designed to closely mirror commercial semiconductor IP deployment while maintaining appropriate intellectual property protection and foundry compliance. Universities execute NDAs and MPW service agreements directly with Muse to access the IP. When a TCI PLL is requested, Muse provides an amendment designating the PLL part number and research project, signed by the authorizing party, before delivering the design kit to the designated university contact.
The structure addresses a friction point in academic chip design that rarely gets discussed: licensing friction from commercial IP vendors typically adds weeks to research timelines while legal teams negotiate terms that don’t fit academic use cases. By pre-negotiating framework agreements, this program eliminates that delay for subsequent projects through simple amendments rather than full contract renegotiations.
Multi-project wafer services let organizations share fixed costs, reducing expenses from millions of dollars to as low as $10,000-$50,000 depending on the process node. The MPW technique reduces the cost of a full prototyping wafer run to 10% or even 5% of the initial price.
TCI offers wide-range multiplier with 1-64 feedback division
The program provides access to TCI’s General Purpose PLL, a wide-range clock multiplier with de-skew capability. The IP contains a 1-16 divider at the reference clock input, a 1-64 divider in the internal feedback path, and a 1-16 divider at the output, with 50% duty cycle outputs for all divider values. These low-jitter PLL hard macros are suited to a wide variety of interface standards and chip applications, and are available for delivery in TSMC, GLOBALFOUNDRIES and UMC processes from 180nm to 4nm.
For this university program, TCI will provide the General Purpose PLL in TSMC 180nm, 65nm, 28nm, and 16nm process nodes—the same processes Muse offers through its MPW program. The PLLs are designed to deliver optimal jitter performance across all multiplication settings, making them suitable for system clock, interface, and general-purpose applications.
AI-assisted portal provides first-level technical support
Students and faculty access user guidelines, application notes, and training videos through a self-service portal on the Muse website. The portal will expand to include general PLL education material and an AI-assisted knowledge base for PLL and IP-related questions. Muse provides first-level support, with True Circuits handling second-level technical assistance.
Many existing VLSI courses rely on closed-source EDA tool licenses and NDA-restricted process design kits, requiring a complex security and access-control infrastructure accessible only to a limited number of educational institutions, which restricts hands-on chip design training to a few selected students or universities. This program follows a different model by making commercial IP available under simplified agreements rather than relying solely on open-source alternatives.
Universities running chip tapeouts through Muse’s MPW service should evaluate whether using pre-qualified commercial PLLs frees up design time for the core research contribution versus building custom clock distribution from scratch. The program’s amendment-based licensing for subsequent projects suggests it’s designed for labs running multiple tapeouts per year, not one-off student projects. Check whether your target TSMC node aligns with the four offered processes before committing to the workflow.
What process nodes does the university PLL IP program support?
The program provides True Circuits General Purpose PLLs in TSMC 180nm, 65nm, 28nm, and 16nm process nodes. These align with the processes Muse offers through its multi-project wafer service. Universities working in other TSMC nodes or alternative foundries will need to source PLL IP separately.
How does MPW pricing compare to dedicated wafer runs for university prototypes?
MPW services reduce expenses from millions of dollars to as low as $10,000-$50,000 depending on the process node. The multi-project wafer technique typically reduces costs to 10% or even 5% of a full prototyping wafer run. The exact price depends on die size, process node, and the number of designs sharing the reticle.
Article Source: Muse Semiconductor and True Circuits Launch PLL IP Access Program for Universities at Low Cost
