- UW-Madison team achieves 2.957/3 score detecting RTL Trojans in gate-level netlists
- LoRD method uses heuristics instead of machine learning feature extraction
- Detection approach exploits stable structural patterns surviving synthesis transformations
- Lightweight technique requires no training data overhead typical of ML approaches
Researchers at the University of Wisconsin–Madison and Marist University scored near-perfect results detecting malicious hardware insertions in synthesized chip designs without the computational baggage of machine learning. Their LoRD method achieved an on-average score of 2.957 out of 3 for Trojan-implanted designs, outpacing transformer-based models and five competing teams in a contest benchmark.
The work, published September 2026, tackles a vulnerability window that opens when register-transfer-level (RTL) code gets translated into gate-level netlists—the blueprint from which physical chips are fabricated. Hardware chip producers often outsource designs to third parties and use computer-aided design tools from different vendors, and the globalization of the CAD tool industry introduces the risk of hardware Trojan insertion by malicious entities.
Trojans leave structural fingerprints after synthesis
The Wisconsin team demonstrated that Trojans planted in high-level RTL code leave predictable fingerprints even after synthesis tools perform optimizations like constant propagation, retiming, and technology mapping. Synthesis engines apply complex optimizations including retiming, technology mapping, and gated-clock insertion, yet formal equivalence checking mathematically verifies that every possible input sequence produces identical outputs across both representations.
LoRD exploits distinctive subgraph signatures in the netlist structure rather than training neural networks on generic features. This approach sidesteps the data collection and hyperparameter tuning that slows ML deployment. Heuristic rules can be applied immediately to new designs without building labeled training datasets from proprietary IP.
Fragmented supply chain multiplies insertion opportunities
The plausible presence of chip-based hardware backdoors can impede technological advancement, eroding trust in innumerable supply chains and hindering global trade, and the complex and fragmented semiconductor supply chain presents many opportunities for inserting hardware backdoors. Malicious actors like rogue employees might attempt to insert Hardware Trojans during manufacturing stages or at any point in the supply chain, and semiconductor manufacturing typically involves numerous subcontractors and suppliers where each additional participant increases the potentiality for vulnerabilities and security gaps.
Hardware Trojans are extremely hard to detect because the scale of alterations is tiny compared with the entire chip design, the nanoscale feature sizes of advanced IC fabrication are challenging to monitor, and conditions that trigger a Trojan circuit are unknown. Detection at the gate-level netlist stage—before physical fabrication—offers a cost-effective checkpoint. Once a wafer is fabricated, vulnerabilities in hardware chips are often non-mitigable after the chips are manufactured.
Heuristics match ML accuracy without training overhead
The contest testcases used by the Wisconsin team represent real-world RTL-to-gate synthesis flows. Competing methods based on graph neural networks and transformers required extensive feature engineering and training cycles. LoRD’s heuristic rules operate directly on netlist topology, identifying signal-flow anomalies that correlate with malicious insertions.
After synthesis, verification at the gate-level netlist is essential to ensure that the hardware implementation matches the functional and timing requirements, and verification engineers use formal, functional, and simulation techniques to check if the design meets the RTL specifications, though post-synthesis verification is much more detailed but also much slower compared to RTL verification. A lightweight detection pass that runs without ML infrastructure could slot into existing equivalence-checking workflows with minimal retooling.
If your gate-level verification flow already includes formal equivalence checks, add a Trojan detection pass before sign-off. Heuristic approaches like LoRD deliver near-perfect accuracy without the training overhead that keeps ML-based security tools confined to research labs. For organizations designing chips with third-party IP or outsourced synthesis, this represents a practical gate before tape-out—especially when detecting modifications invisible to traditional functional verification.
Why is gate-level netlist the critical detection point for hardware Trojans?
Gate-level netlists are the last design artifact before physical layout and fabrication. Detecting Trojans here catches malicious insertions introduced during RTL design or synthesis tool manipulation, while post-fabrication detection faces the challenge that chip modifications are permanent and hardware alterations at nanoscale are nearly impossible to spot through physical inspection alone.
How do heuristic methods outperform machine learning for Trojan detection?
Heuristics leverage known structural patterns—like unusual signal-flow paths or rare gate combinations—that Trojans create in netlists. These patterns remain stable across synthesis optimizations. Machine learning requires large labeled datasets of Trojan and clean designs for training, plus tuning for each new design family, while heuristics operate immediately on any netlist topology without prior data collection.
Article Source: Detecting Hardware Trojans in Synthesized Gate-Level Netlists (UW-Madison, Marist)
