- SPIL broke ground on $3.1B CoWoS packaging plant in Taiwan
- YMTC reached 14% NAND shipment share, claiming third place globally
- Co-packaged optics faces production reliability challenges amid rapid deployment
- Intel raised $20B in stock offering to fund growth
SPIL, ASE’s subsidiary that handles AI-chip packaging for Nvidia and offers CoWoS services, broke ground on a nearly $3.1B advanced packaging and test facility in Douliu, Taiwan. The 6-hectare plant targets first-phase production in 2028 and will create more than 2,200 jobs. AI workloads are shifting from training to inference, pushing enterprise SSDs to 48% of total NAND bits shipped and driving NAND industry revenue up fivefold from Q2 2024.
TSMC’s CoWoS capacity remains tight into 2026, pushing Taiwan’s major OSAT providers including SPIL to accelerate advanced packaging expansion to secure AI-related orders. SPIL is accelerating expansion with its fifth factory acquisition this year, spending more than NT$22.7 billion on factory acquisitions so far in 2026.
YMTC overtakes Kioxia in NAND shipments
According to Counterpoint Research figures published August 12, 2026, YMTC accounted for 14% of globally shipped NAND bits in the second quarter, rising to third place for the first time. Samsung led shipments with 25%, down from 32% in Q2 2024 as it prioritized high-margin DRAM, while SK hynix held second at 22% on a 40% quarter-over-quarter jump in Solidigm bit shipments. YMTC now narrowly edges out Kioxia and Micron by volume.
YMTC ranked third in shipments but closed fifth in revenue, behind Micron and Kioxia, because its product mix is still concentrated in consumer applications with a low share of high-priced data-center eSSDs. The company is moving an enormous quantity of flash and earning relatively little per bit, because nearly all of it is consumer-grade: client SSDs, phone storage, memory cards. YMTC grew shipments 22% year over year while mass-producing 267-layer 3D NAND on its Xtacking architecture, and its third Wuhan fab has cleared Beijing’s 50% domestic-tooling threshold with production due late this year.
The real story is how completely the market has shifted. While YMTC climbs volume rankings, the money has moved to enterprise SSDs that now consume nearly half of all NAND production. Counterpoint expects enterprise SSDs to cross 50% of total bits by year-end. That structural shift helps explain why memory makers are deliberately limiting NAND investment in favor of higher-return HBM and DRAM—a strategy that’s prolonging tight NAND supply even as total bit shipments grow. The gap between shipment share and revenue share reflects a two-tier market: hyperscale buyers paying premium prices for eSSDs that hold key-value caches and inference datasets, and everyone else fighting over consumer-grade flash at a fraction of the margin.
Co-packaged optics faces serviceability and ecosystem barriers
A 19-company coalition within the Open Compute Project unveiled a plan for standardized silicon photonics-ready infrastructure for AI systems, and data-center network fabrics are shifting architectures as optical interconnects assume a larger role in AI-cluster connectivity. But co-packaged optics (CPO) is struggling with the jump from lab instrumentation to production automated test equipment on factory floors.
CPO adoption depends on proving robust, multi-vendor business models along with clear advantages in cost, power, and scalability at the system level, while key ecosystem elements—including standardized optical interfaces, reusable IP blocks, and interoperable test and qualification flows—are still coming together. Because optical engines and high-value switching or processing chips are integrated within the same package, a failure in the optical subsystem could require replacing an entire CPO board rather than a single component, increasing maintenance costs.
A broad range of skill sets are required, with experts in power delivery, cooling, cable management, connectors, and optics needing to work in concert to build dense systems and develop technologies to make deploying and servicing these unique systems a repeatable process. The push toward 1-megawatt racks is forcing changes in data center architecture, including cooling, power delivery, rack design, and 3D-IC packaging—all of which CPO must integrate with before it can move beyond prototype deployments.
Capacity expansions and capital raises
Lam Research committed $3B over five years to expand its R&D lab network, increasing experiment capacity by more than 50%. The company is also partnering with NY Creates to train about 3,500 university students in semiconductor process integration over the next five years, deploying Lam’s SEMulator3D virtual fabrication software across colleges and universities in NY Creates’ Northeast workforce-development network.
Sony Semiconductor and TSMC signed a deal on their next-gen image sensor joint venture in Japan. Sony will contribute about ¥465B (~$2.9B) and control the venture, while TSMC will contribute about ¥282B (~$1.8B). The Kumamoto operation is expected to begin volume production of smartphone image sensors in 2029, pending regulatory approvals.
Intel raised $20B in an upsized base stock offering. The company said the capital positions it to meet growth opportunities ahead. Nvidia’s new plan to mobilize $500B in third-party capital for AI infrastructure is getting mixed reviews—some say it can extend the AI spending cycle with outside investors bearing most of the risk, while others question whether depreciating GPUs can be long-term infrastructure assets.
Watch YMTC’s revenue trajectory, not just shipment share. The company’s third-place ranking in NAND bits shipped means little if it stays locked out of the enterprise SSD market where margins are 3-5x higher. The real test is whether YMTC can break into Western server qualification—currently blocked by Entity List restrictions—or whether it remains a consumer-grade volume player subsidizing the market with low-margin bits. For procurement teams, this creates a two-speed NAND market: tightening supply and rising prices for enterprise-grade flash, and a growing glut of consumer inventory that won’t solve data-center bottlenecks.
Why is co-packaged optics deployment lagging despite industry support?
CPO integrates optical engines directly with switch ASICs, which improves performance but creates a serviceability problem: if the optical subsystem fails, the entire board—including expensive switching chips—must be replaced rather than swapping a pluggable module. Standardized optical interfaces, interoperable test flows, and field-replaceable designs are still in development. Production automated test equipment also hasn’t caught up with CPO’s shift from lab prototypes to factory-floor volumes.
What’s driving the gap between YMTC’s shipment share and revenue?
YMTC ships 14% of global NAND bits but ranks fifth in revenue because nearly all its output goes to consumer applications—client SSDs, phones, memory cards—that sell for a fraction of what hyperscalers pay for enterprise SSDs. Enterprise SSDs now absorb 48% of all NAND bits shipped, up from 26% a year ago, and command margins several times higher. YMTC remains on the US Entity List, which blocks it from Western server qualification where the revenue is concentrated.
Article Source: Chip Industry Week In Review
