- Intel ships Panther Lake processors using High-NA EUV on 18A layers
- UMC delivers first mass-production silicon photonics wafers from Singapore fab
- JEDEC releases SPHBM4 standard enabling HBM4-class memory on organic substrates
- TSMC plans $100B for U.S. fabs; Intel adds €5B Ireland expansion
Intel Foundry is manufacturing a subset of Panther Lake processors using ASML’s High-NA EUV system on selected Intel 18A layers, marking the first high-volume logic product on High-NA EUV. The layers are dual-qualified, meaning the same layer can be exposed on either a 0.33 NA NXE scanner or a 0.55 NA EXE scanner, with resulting wafers being interchangeable. A High-NA system costs around $400 million, roughly twice that of conventional EUV.
Silicon photonics hits high-volume production across three foundries
UMC announced first mass-production wafer delivery of photonic ICs from its Singapore fab, supporting SILITH’s 1.6T silicon photonics platform for AI optical interconnects. The partners brought the platform from development to production readiness in just 18 months. UMC will make its own 12-inch silicon photonics platform available for customer product development in 2027.
Tower Semiconductor’s Japan expansion for silicon photonics, silicon germanium, and advanced packaging is forecasted at approximately $3 billion in Tower investment, net of $1 billion in grants from the Government of Japan. TSMC, GlobalFoundries and Tower Semiconductor have expanded silicon photonics capabilities in recent years as demand for AI networking hardware accelerates.
Data movement between chips now consumes more power and creates more latency than the computation itself. As silicon photonics wins more market share, each module still requires an InP laser, yet the InP epitaxy supply chain is far narrower than silicon photonics foundry capacity, making this the next critical constraint. Foundries betting billions on photonics capacity risk building fabs that outrun their ability to source the indium phosphide light sources every optical module requires.
HBM4 standard splits into two packaging approaches
JEDEC finalized JESD330-4, the SPHBM4 standard, which uses the same DRAM dies as HBM4 with a new interface base die that enables mounting on standard organic substrates rather than silicon substrates. SPHBM4 is architected to operate at the same aggregate data throughput as HBM4 using fewer pins by operating at a higher frequency. SPHBM4 cut pins to 512 and widened the spacing, so memory attaches directly to the organic substrate without going through a silicon interposer.
The standard supports bump pitches greater than 90 µm and channel reaches up to 20 mm, enabling use of less-expensive organic substrate routing. With SPHBM4 on an organic substrate, three memory devices can be connected along the same edge, increasing both memory capacity and bandwidth by approximately 50% compared to silicon interposer layouts.
Capacity expansions concentrate in U.S. and Asia
TSMC announced an incremental $100 billion investment in advanced semiconductor manufacturing and packaging facilities in Arizona, potentially expanding its footprint to about 12 U.S. fabs and packaging facilities. Intel Foundry will invest €5 billion to expand Intel 3 capacity at its Leixlip, Ireland campus. Samsung plans to begin operations at its first Yongin semiconductor fab by 2029, speeding up the original schedule by one to two years.
India’s government approved approximately $13.2 billion for Semicon 2.0, covering chip design, equipment and materials, new fabs, advanced packaging, R&D, and workforce development. The European Commission approved €659 million in German subsidies for four new facilities producing silicon carbide epi-wafers, power MOSFETs, semiconductor metrology equipment, and specialized detector chips. The U.S. Commerce Department will provide Bosch CHIPS Act incentives worth up to $225 million to help pay for a $2 billion conversion of its Roseville, California, facility into a silicon carbide chip fab.
Nanya Technology plans to invest about $16 billion in its new Taiwan DRAM fab—up from the $9.4 billion originally planned—with the first phase expected to reach 30,000 wafer starts per month by 2028. Chinese DRAM maker CXMT’s $8.55 billion Shanghai IPO was more than 200 times oversubscribed by retail investors, while U.S. lawmakers urged the Commerce Department to prohibit U.S. purchases of CXMT and other Chinese memory companies.
Intel’s High-NA production deployment on Panther Lake demonstrates the technology works in volume manufacturing, but the dual-qualification strategy reveals the real challenge: $400 million lithography tools need to justify their cost against conventional EUV systems that produce interchangeable wafers. Foundries expanding silicon photonics capacity should verify their InP laser supply chains can scale at the same rate as their wafer fabs, or risk building stranded capacity. SPHBM4’s organic substrate approach trades some signal integrity for lower packaging costs and higher memory density per package—a tradeoff that makes sense for applications where absolute peak bandwidth matters less than bandwidth per dollar.
Why does SPHBM4 use organic substrates instead of silicon interposers?
Reducing pin count allows wider spacing between contacts, which enables connection to organic substrates rather than silicon interposers—silicon substrates support pitches above 10 micrometers, while organic substrates operate closer to 20 micrometers and cost less to manufacture. By eliminating the need for silicon interposers, SPHBM4 enables manufacturers to use mature organic substrate technologies instead of scarce silicon interposers, addressing advanced packaging capacity constraints.
What percentage of Intel’s Panther Lake processors use High-NA EUV lithography?
Intel is currently using High-NA technology only for selected layers and a portion of Core Ultra Series 3 production. Intel has not identified which retail models or processor batches use High-NA-patterned layers. Layers are dual-qualified on both High-NA and conventional EUV platforms, with resulting wafers being interchangeable, so the percentage varies based on manufacturing allocation rather than product differentiation.
Article Source: Chip Industry Week In Review
