- First-silicon success rate fell to 14% in 2024, down from 32% in 2020
- Communication efficiency now defines AI infrastructure performance, not peak compute
- CFET transistors achieve 46% area reduction compared to N2 reference designs
- Backside power delivery separates power and signal networks to improve density
First-silicon success dropped to 14% in 2024, down from 32% in 2020 and 24% in 2022. (cite index=”20-6″>The rate declined 53 percent between 2020 and 2024, the steepest fall in two decades of tracking the metric. (cite index=”21-11″>Only 14% of ASIC/SoC projects achieved first-silicon success — the lowest figure in more than twenty years. Harry Foster at Siemens EDA notes that 75% of projects now run behind schedule.
Verification capabilities lag behind design complexity
Verification capabilities have improved, yet success rates have collapsed. Chiplet integration, advanced packaging, and multi-die assemblies have driven complexity far beyond what traditional verification methodologies can handle. (cite index=”21-10″>Advanced packaging, chiplet-based integration, EUV lithography variability, power integrity, and high-speed protocol complexity have all contributed to the industry-wide decline in first-silicon success.
Companies have added verification engineers and adopted new EDA tools, but (cite index=”22-4″>notwithstanding incremental improvements in EDA tools, design success rates have kept worsening over the past several years. Modern designs require more verification state space than teams can cover before tapeout, even with automation.
What makes this crisis different from past verification challenges is the speed and magnitude of decline. The industry maintained roughly 30% first-silicon success from 2010 through 2020, absorbing complexity increases through brute-force engineering. That approach stopped working in 2020. The underlying issue is that traditional measures of verification completion—coverage metrics, simulation cycles, formal checks—don’t capture system-level interactions that cause silicon failures. Engineers can hit 100% code coverage and still miss critical bugs that emerge only when multiple subsystems interact under specific timing conditions.
AI infrastructure shifts from compute to communication bottlenecks
Cadence’s Mayank Bhatnagar points out that AI infrastructure has fundamentally diverged from traditional data center design. Performance no longer comes from peak compute capability but from communication efficiency determined by the underlying IP architecture. (cite index=”30-5″>With the growth in both model training volume and per-GPU computational capability outpacing the interconnect capabilities, communication has emerged as the principal performance bottleneck.
(cite index=”29-1″>AI workloads demand ultra-high speed, low-latency communication, often between thousands or even millions of interconnected processing units. Scale-up networks connecting dozens of GPUs within a rack use low-loss copper and protocols like NVLink, while scale-out networks distributing workloads across data centers face different constraints entirely. (cite index=”33-11″>An AI data center backend network must support high-bandwidth, low-latency east-west traffic between compute nodes, ensuring synchronized communication to prevent GPU idling.
CFET transistors and backside power target angstrom-era scaling
Synopsys researchers Ravi Todi, Urmimala Roy, and Xi-Wei Lin examine the current state of gate-all-around (GAA) transistors and the path forward to complementary FETs (CFETs). (cite index=”8-13″>GAA has moved from early adoption into the mainstream of leading-edge design, and the industry’s attention is already turning to what comes after it. (cite index=”8-3″>Recent work demonstrated 3.5-track CFET designs in A7 (7 Å technology equivalent) reaching 46% area reduction compared to their N2 (2nm technology equivalent) reference, while keeping performance the same.
(cite index=”5-4,5-5″>A complementary field-effect transistor (CFET) utilizes GAAFETs vertically stacked on top of one another to reduce the amount of space required, with GAAFETs of opposite polarity vertically stacked. The technology becomes viable when combined with backside power delivery. (cite index=”9-1,9-2″>Backside power delivery refers to the technique of routing power supply lines on the backside of a semiconductor chip instead of the traditional frontside, which increases logic density and improves power and performance.
(cite index=”14-13″>Power interconnects increasingly compete for space in the complex BEOL network and account for at least 20 percent of the routing resources. Moving power to the backside frees frontside resources for signal routing and enables more aggressive standard cell height scaling, directly supporting the density gains needed to make CFET economically viable.
The collapse in first-silicon success reveals a structural problem that won’t be solved by incremental tool improvements or adding verification engineers. Companies need to fundamentally rethink how they measure verification completeness before tapeout. Traditional coverage metrics miss system-level interactions that cause the majority of silicon failures. Until the industry develops better predictive models for where bugs actually occur in complex multi-die systems, expect success rates to remain depressed even as individual tools improve.
What is causing the sharp decline in first-silicon success rates?
The primary driver is the shift to multi-die chiplet architectures and advanced packaging, which create exponentially more verification state space than traditional monolithic designs. Chiplet integration, heterogeneous die stacking, and high-speed serial interconnects introduce system-level interactions that don’t appear in component-level verification but cause failures in silicon.
How does backside power delivery improve chip performance?
Backside power delivery routes power supply lines on the silicon wafer backside rather than the frontside, freeing up roughly 20% of frontside routing resources for signal interconnects. This separation reduces IR drop, allows thicker low-resistance power rails, and enables more aggressive standard cell scaling by eliminating the area overhead of traditional in-cell power rails.
Article Source: Blog Review: Aug. 26
