Research institute imec and semiconductor equipment manufacturer EV Group have demonstrated wafer-to-wafer hybrid bonding technology at 200 nanometer copper interconnect pitch with unprecedented overlay accuracy, a critical advancement for next-generation chip architectures requiring extreme interconnect density. The breakthrough, presented at the 2025 IEEE Electronic Components and Technology Conference, marks a significant step toward realizing imec’s CMOS 2.0 scaling paradigm for future compute systems.
The achievement centers on a copper pad-to-pad post-bond overlay vector below 40 nanometers across 100% of dies on full 300mm wafers—a world-first accomplishment. This exceptional precision was enabled by EVG’s GEMINI FB wafer bonding system, which proved essential for ensuring high electrical yield in these ultra-fine-pitch applications.
Technical Process Optimization
The robust bonding technology was validated on test vehicles containing four layers of routable interconnects pre-processed on each wafer before bonding. According to Zsolt Tokei, imec fellow and program director of 3D system integration, success required co-optimizing multiple critical elements including the use of SiCN dielectric material pioneered by imec and chemical mechanical polishing optimized for high across-wafer uniformity.
The CMP process produces extremely flat dielectric surfaces while achieving controlled nanometer-scale recess for copper pads. Enhanced overlay control was further facilitated through improved copper pad design and pre-bond lithography corrections.
Roadmap for Advanced Applications
The 200nm pitch technology addresses requirements for logic-to-logic and memory-to-logic tier stacking in CMOS 2.0 architectures, where system-on-chip designs are partitioned into heterogeneous functional tiers reconnected through 3D interconnect technologies. Imec intends to push the roadmap below 200nm pitch with continued collaboration with EVG.
Paul Lindner, executive technology director at EV Group, emphasized that the partnership reflects three decades of collaboration demonstrating how equipment suppliers and research organizations can drive meaningful process technology advances.
Key Takeaway
The demonstration of 200nm pitch wafer-to-wafer hybrid bonding with sub-40nm overlay accuracy establishes a new benchmark for 3D semiconductor integration, enabling the interconnect densities required for advanced logic partitioning in future high-performance computing architectures while maintaining manufacturing yield across full production wafers.
Article Source: Imec and EV Group Demonstrate Wafer-to-Wafer Hybrid Bonding with 200nm Interconnect Pitch and Record High Overlay Accuracy
